1. Field of the Invention
The present invention generally relates to video image processing and, more particularly, to an image buffer architecture which is capable of providing multiple image frames or "snapshots" simultaneously, either to a plurality of image processors or to multiple locations within a computer system, providing a highly flexible image data input/output buffering system.
2. Description of the Prior Art
Image capture and processing systems are used in a diverse variety of systems from manufacturing inspection systems to multimedia presentation systems. Typically, such systems employ a video camera to generate an analog signal of a raster scanned image. One or more frames of this analog signal is digitized and stored in an image buffer. The combination of the analog-to-digital (A/D) converter and the image buffer is often packaged on a single printed circuit board (PCB) and sold in the trade as a "frame grabber", meaning that the board is capable of "grabbing" (i.e., storing) a video frame. A portion of a stored frame, termed the region of interest (ROI), may be addressed and read out for processing.
In an inspection system, an object may be scanned a number of times to provide a sequence of frames. The image processor analyzes the data which constitutes the ROI in each frame as a series of "snapshots" in order to detect and provide information indicative of selected variations within the ROI. In this way the locations of object defects are determined. In a multimedia system, the scanned image may be manipulated, enhanced or converted, depending on the final presentation format.
In current image processing systems, the video frame buffer (i.e., frame grabber cards) are a speed bottleneck to overall system performance. Two things affect the transmission of the video image data; the architecture and bandwidth of the video frame buffer and the bandwidth of the data bus or local area network (LAN) used to communicate the image data. The fundamental flaw in the prior art is in the video frame buffer architectures. Current frame buffers place the burden of bandwidth limitations in the data bus and/or the LAN by transporting image data in and out of various boards and/or memory along the data bus or LAN serially.
A typical configuration is illustrated in FIG. 1, in which a video camera 10 provides an analog video signal to a frame grabber 11 which digitizes and temporarily stores a frame of video data. This digitized video data is supplied via the data bus 12 of a personal computer (PC) to other functional components which are also interfaced with the bus 12. The bus 12 may be any of the several industry standards such as the Microchannel bus of IBM PS/2 PCs, the so-called ISA (for industry standard architecture as adopted by the IEEE) bus or the EISA (for extended ISA) bus. The digitized data from frame grabber 11 is delivered via bus 12 to a data compression card 13 which, in turn, outputs compressed data, again via bus 12, to the central processor unit (CPU) random access memory (RAM) 14. The data in RAM 14 may be displayed by sending it, via bus 12, to the display adapter card 15 which drives a display device 16, such as a cathode ray tube (CRT) monitor. In addition, the image data in RAM 14 may be transmitted on a local area network (LAN). To do so requires that the data in RAM 14 be transferred, again via bus 12, to a LAN adapter card 17 which formats the data into packets for transmission.